The present invention relates generally to reducing dislocations in semiconductor structures. More specifically, the invention is directed to processes for reducing dislocations in semiconductor layers formed on a dissimilar substrate. The invention is further directed to dislocation reduction in heteroepitaxial semiconductor structures (i.e. semiconductor layers of one material formed on a semiconductor layer of a different material).
Substrates (also called wafers) on which semiconductor devices can be fabricated can be formed from a variety of materials. By way of example, some substrates are formed from gallium arsenide (GaAs), while others are formed from indium phosphide (InP) or silicon (Si). Different substrate materials have different advantages and disadvantages. For example, substrates formed from GaAs and InP are relatively fragile, in relation to those formed from Si of the same thickness. Due to the fragility, GaAs and InP substrates need to be thicker than Si substrates to make fabrication practical. Because GaAs and InP substrates tend to be thicker and have a higher density than Si substrates, they are heavier than Si substrates having the same surface area. Additionally, Si substrates are much less expensive than GaAs or InP substrates.
As in the case of substrates, the semiconductor devices fabricated thereon can also be formed from a variety of materials. By way of example, both InP and GaAs are suited for fabrication of photovoltaic cells, also called solar cells when used with sunlight. InP and GaAs are also suited for fabrication of optoelectronic integrated circuits (OEIC), wherein optical devices, such as laser diodes and photodiodes, are fabricated together with semiconductor transistors on a common substrate. Such fabrication can entail depositing layers of epitaxial films (films having a predominately single crystallographic orientation) on dissimilar substrates. By this we mean that the epitaxial film can be one type of semiconductor, for example InP or GaAs, while the substrate wafer can be a different semiconductor, such as Si or germanium (Ge). Epitaxial films are sometimes referred to as epilayers, and formation of an epitaxial film on a dissimilar substrate is typically referred to as heteroepitaxy.
To take full advantage of particular unique properties of various materials, it is sometimes desirable to fabricate electronic devices and the substrate on which they are formed from dissimilar semiconductors. However, such heteroepitaxial fabrication poses significant difficulties, such as dislocations which can thread through adjacent layers, epitaxial layer cracking and surface roughness. These difficulties are caused predominantly by differences in the lattice constants and in the linear coefficients of thermal expansion of the dissimilar materials employed. For example, the lattice constant of Si (5.43 angstroms) differs from that of GaAs (5.65 angstroms) by approximately 4%, and the thermal expansion coefficient of Si (3.times.10.sup.-6 .degree. C..sup.-1) differs from GaAs (6.times.10.sup.-6 .degree. C..sup.-1) by a factor of two. Similarly, the lattice mismatch between InP (lattice constant of 5.87 angstroms) and Si is approximately 8% and the thermal expansion coefficient of InP (5.times.10.sup.-6 .degree. C..sup.-1) differs from that of Si (3.times.10.sup.-6 .degree. C..sup.-1) by a factor of about 1.7.
A variety of prior art processes exist for minimizing the density of dislocations in heteroepitaxial structures. One such prior art process forms an amorphous buffer layer between a substrate and an epitaxial layer of a dissimilar material. According to one example of this process, an amorphous GaAs buffer layer is formed on a Si substrate, followed by an amorphous InP layer and then an epitaxial InP layer. Since the GaAs buffer layer has a lattice constant intermediate between the lattice constants of the Si substrate and the InP layers, it serves to ease the transition between the substrate and the epitaxial layer.
Another prior art process for easing the transition between the substrate and the epitaxial layer of a dissimilar material lies in the use of a compositionally graded interface between the substrate and the epitaxial layer. Preferably, the graded interface is lattice matched to the substrate at one end and lattice matched to the material of the semiconductor device at an opposite end. The compositional grading is achieved by gradually adding or subtracting a component to a base substance as the graded interface is formed on the substrate, thus allowing a smooth compositional transition between the substrate material and the epitaxial layer material.
A further prior art process employs interrupted growth. According to this process, a plurality of epitaxial layers of a semiconductor composition are formed at an elevated temperature (for example, 700.degree. C. in the case of InP epitaxy) on a dissimilar substrate. Following the formation of each layer, the substrate and previously formed layers are cooled. Due to lattice mismatch between the epitaxial layers and the substrate, initially a high concentration of dislocations exist. However, since the thermal expansion coefficients of the epitaxial layers and the substrate are different, the epitaxial layers are subjected to mechanical stresses during cooling. The mechanical stresses induce dislocation movement and cause the dislocations to form loops. The dislocation loops tend not to thread through to any subsequently formed layers.
Although prior art processes have achieved some success with regard to reducing threading dislocations in heteroepitaxial semiconductor structures, there is nevertheless room for improvement. Specifically, it is difficult to achieve reproducible results with prior art processes, thus rendering commercialization of heteroepitaxial semiconductor structures costly.
Accordingly, an object of the present invention is to provide an improved process for fabricating semiconductor epitaxial layers on dissimilar substrates.
A further object of the present invention is to reduce threading dislocations in heteroepitaxial semiconductor structures.
Another object of the present invention is to provide a process for reproducibly fabricating heteroepitaxial semiconductor structures having a reduced density of dislocations.
Other objects of the invention will in part be obvious and in part appear herein after.